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Functional verification
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#	Item
51	White Paper Benefits of Using ESP in Memory Designs May 2010 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-04 07:15:42 Hardware description languages Logic design Logic simulation VHDL Standard cell Functional verification SPICE Verilog Simulation Electronic engineering Electronic design automation Digital electronics
52	Datasheet Memory Solution Overview Memory products are among the most Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 12:43:58 Integrated circuits Hillsboro Oregon Synopsys Electronic design automation Physical design Integrated circuit design Parasitic extraction Functional verification Signoff Electronic engineering Electronics Electronic design
53	Datasheet VCS Functional Verification Choice of Leading SoC Design Teams Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:41:22 Hardware description languages SystemVerilog OpenVera E Functional verification Synopsys Open Verification Methodology Verilog Logic simulation Electronic engineering Electronic design automation Hardware verification languages
54	Synopsys Professional Services Datasheet SoC Integration & Verification At-A-Glance `` Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 12:40:10 Hillsboro Oregon Synopsys SystemVerilog Physical design Functional verification E OpenVera Virtual Socket Interface Alliance Electronic engineering Electronic design automation Hardware verification languages
55	Datasheet Mobile Devices Solution Overview Designers face numerous challenges in developing the systems and ICs needed for today’s leading-edge mobile Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 12:44:17 Electronic design automation Electronic design Hillsboro Oregon Synopsys Integrated circuit design High-level synthesis Field-programmable gate array Functional verification Application-specific integrated circuit Electronic engineering Electronics Integrated circuits
56	Formal verification of a realistic compiler Xavier Leroy INRIA Paris-Rocquencourt Domaine de Voluceau, B.P. 105, 78153 Le Chesnay, France Add to Reading List Source URL: pauillac.inria.fr Language: English - Date: 2009-04-07 07:40:29 Compilers Programming language implementation Functional languages Formal methods Compiler correctness Compiler Compcert Xavier Leroy Code generation Software Computing Compiler construction
57	A Programmer-Centric Approach to Program Verification in ATS∗ Zhiqiang Ren1 and Hongwei Xi1 1 2 Add to Reading List Source URL: cs-www.bu.edu Language: English - Date: 2013-10-14 02:11:12 Data types Functional programming Functional languages Procedural programming languages Lisp programming language ATS Fold Append ML Software engineering Computing Computer programming
58	A Programmer-Centric Approach to Program Verification in ATS∗ Zhiqiang Ren1 and Hongwei Xi1 1 2 Add to Reading List Source URL: www.cs.bu.edu Language: English - Date: 2013-10-14 02:11:12 Data types Functional programming Functional languages Procedural programming languages Lisp programming language ATS Fold Append ML Software engineering Computing Computer programming
59	Manuel Hermenegildo Areas of Interest Energy-Aware Computing, Resource / non-functional property analysis, verification, and control; Global Program Analysis, Optimization, Verification, Debugging; Abstract Interpretatio Add to Reading List Source URL: www.clip.dia.fi.upm.es Language: English - Date: 2014-07-12 00:42:10 Programming paradigms Formal sciences Association for Computing Machinery Principles of Programming Languages Formal methods International Conference on Logic Programming Logic programming International Symposium on Logic-based Program Synthesis and Transformation Lecture Notes in Computer Science Computer science Computing Software engineering
60	White Paper Understanding DO-254 Compliance for the Verification of Airborne Digital Hardware October 2009 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-05-07 08:15:40 Integrated circuits Formal methods DO-254 Functional verification Logic simulation Electronic design automation Integrated circuit design Formal equivalence checking Synopsys Electronic engineering Electronics Electronic design

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